Запропоновано проект мікропроцесорної архітектури, заснованої на принципі мінімізації апаратури і орієнтованої на ефективну паралелізацію. Постульовано поняття групи машинних інструкцій, яка формується інтелектуальним компілятором. Головна інструкція групи вказує, скільки інструкцій група містить для паралельного виконання. Розроблено концепцію флакса як агрегата, що складається з потоків інструкцій та даних, підтримуваних апаратно. Флакс призначено для паралелізації на більш високих рівнях. Формати характерних інструкцій розглянуто на прикладах. Розроблено новий метод управління циклами, які мають числовий параметр, і новий метод паралелізації розгалужень. Запропонована архітектура не містить одночасної багатопотоковості, перейменування регістрів, переупорядкування інструкцій, позачергового виконання, випереджувального виконання, суперскалярного виконання, відкладеного розгалуження, прогнозування розгалужень, всього того, що потребує складної апаратури. Все це заміщується поняттям групи інструкцій, концепцією флакса, спеціальними інструкціями і істотною компіляторною підтримкою.

A RISC microprocessor architecture that realizesa specific method of parallelism including the instruction level parallelism has been considered. The processor has been provided for 4-bit data type tag in each register of the register file. There are 14 data type tag values. The zero data type tag indicates that the register is free, otherwise it is busy. The destination register inherits the data type tag from the first source register. After an operation the data type tags in the source registers may be either zeroed, or may remain unchanged for further usage. All machine operations are classified into computational operations (about 40), and auxiliary operations (about 35 - 45). The computational operations include integer, unsigned, floating point, logical, string, and conversion operations. The processor has specific instruction formats in which there are 6-bit fields both for the operation code and the computational code. A single primary computational instruction having zero in the operation code field, and a meaningful code in the computational code field is enough to express all computational operations. A compiler generates groups of instructions to perform in parallel, the reordering of instructions may take place. There are several clones of the primary computational instruction with operation codes differing from zero. A clone computational instruction with a certain operation code is placed as a header instruction for the instruction group pointing out a certain number of instructions in the group to issue in parallel. The primary instructions may be placed inside the groups. The concept of flux is introduced as a composite of stream of instructions and a flow of processed data maintained by the flux hardware. Fluxes improve the usage of multiple functional units, and may be used for further parallelization.

A RISC microprocessor architecture that realizesa specific method of parallelism including the instruction level parallelism has been considered. The processor has been provided for 4-bit data type tag in each register of the register file. There are 14 data type tag values. The zero data type tag indicates that the register is free, otherwise it is busy. The destination register inherits the data type tag from the first source register. After an operation the data type tags in the source registers may be either zeroed, or may remain unchanged for further usage. All machine operations are classified into computational operations (about 40), and auxiliary operations (about 35 - 45). The computational operations include integer, unsigned, floating point, logical, string, and conversion operations. The processor has specific instruction formats in which there are 6-bit fields both for the operation code and the computational code. A single primary computational instruction having zero in the operation code field, and a meaningful code in the computational code field is enough to express all computational operations. A compiler generates groups of instructions to perform in parallel, the reordering of instructions may take place. There are several clones of the primary computational instruction with operation codes differing from zero. A clone computational instruction with a certain operation code is placed as a header instruction for the instruction group pointing out a certain number of instructions in the group to issue in parallel. The primary instructions may be placed inside the groups. The concept of flux is introduced as a composite of stream of instructions and a flow of processed data maintained by the flux hardware. Fluxes improve the usage of multiple functional units, and may be used for further parallelization.

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